Register Transfer Level Simulation Acceleration via Process Migration

In this paper we see an approach to hardware acceleration of register transfer level simulations that utilizes Virtual Machines (VMs) and Real Machines (RMs), each executing the same instruction set. Hardware Description Language code for digital designs can lend itself well to parallel execution, and we leverage that property by executing as many processes as possible in RMs in parallel. Since simulation characteristics often change as simulations progress, we need the ability to migrate idle processes out of hardware and busy ones into it. The migration of state from one to the other will utilize run-time reconfiguration of a field-programmable gate array, and in order to maximize the number of RMs in the device, each can be reconfigured to support only the instructions its process requires.